Row syncronization discovered during wade through firmware Additional eyes (both brite and otherwise) requested to confirm this discovery.
According to a SMaL/Cypress/Sensata document, the image sensor (which may or may not hold true for the pv2 image sensor) has data bus and a ROW signal for output. It also states that the ROW signal stays HIGH for one SCLK period during a row time and during that time the system must stop reading data from the sensor.
It goes on to say when ROW is HIGH is a good time to write data to the image sensor program registers.
Looking at the firmware it seems that $fa1f is the ROW signal and while it remains HIGH, the image sensor program registers ($fa24, $fa1d, $f90c, $fa24) are written to.
"When ROW falls, the most recently converted row of pixels
may be read out of the row buffers by the system." This appears to be happening around the section of bank8 that is commented "increment h-loop variable"
I'll have to temporarily abort my wade through the firmware, but your eyes may be interested in looking at the differences in the code surrounding the reading of the ROW signal ($fa1f) of the pv2s vs FF2 and FF3.
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